2D proces and device simulators have been used to predict the performance of scaled MOSFET spanning the 035-[Mu]m to 007-[Mu]m generations.

2D proces and device simulators have been used to predict the performance of scaled MOSFET spanning the 035-[Mu]m to 007-[Mu]m generations. Requirements for junction measure and channel doping are discussed. Constant-field scaling is assumed. MOSFET drive present remains nearly constant from single generation to the next and mostly of the performance improvement proceeds form the decreasing supply voltage. Gate delay decreases at 30% per generation, nearly the same sweep as previous generations. However, this performance gain approachs at the price of earnestly higher off-state leakage because of the reduction of the doorsill voltage. Various solutions to this high leakage are discusses.

Hewlett Packard adopted CMO technology in the mid-1970s. At that time the gate longitudinal dimensions [L.sub.g] was 4 [Mu]m and the gate oxide thickness [Tsubox] was 50 nm Since then, each novel generation of technology has shrivelled [L.sub.g] by about 30% and [Tsubox] by the agency of about 25%. The decrease in [Lsubg] has been tied to the evolution of lithography equipment. Following these scaling stretchs intrinsic gate delay has decreased about 30% by generation. New generations of technology are released about each three years. The important principle in MOSFET scaling is that [Lsubg] and [Tsubox] must decrease together. Scaling single in kind without the other does not yield adequate performance improvement.

The performance metric for gate delay is CV/I, where C is the load capacitance, V is the stock voltage ([V.sub.dd]), and I is the drive rife of the MOSFETs (average of NMO and PMOS) C is compos of one as well as the other gate and junction capacitance. MOSFET scaling, which decreases [Lsubg] [Tsubox] and junction area while increasing substrate doping, attends to keep C fairly constant from generation to generation. For several generations of technology, the take the place of voltage was held constant at 5V (constant-voltage scaling). In that era, gate delay was reduc through ever-increasing MOSFET drive currents. Since the voltage was held constant while the dimensions decreased, the electric fields continuously increased. High fields and high populars tend to damage the gate oxide and lead to device deterioration. Thus, single of the main technology challenges has been to design MOSFET with adequate reliability.

Constant-voltage scaling conclusioned as [L.sub.g] approached 0.5 [Mu]m and [Tsubox] neared 10 nm The demands of gate oxide reliability required that the minister voltage be reduced. This occurr as the peak oxide field reached roughly 4 MV/cm We are now in an era where give voltage is scaled along with [Tsubox] likewise that the peak oxide electric field remains roughly constant (constant-field scaling). This studious mood examines some of the implications for this of exemplar scaling in future technology generations.

Proces and Device Simulations

The 2D proces simulator TSUPREM-4 from Technology Modeling Associates Inc. of Sunnyvale, California was used to simulate scaled MOSFET device mode of buildings The inputs to TSUPREM-4 are the implant and oxidation grades that would be used in the actual proces The proces architecture assumed is similar to circulating CMOS processes, employing shallow source/drain extensions and deeper main source/ drain regions followed from silicidation.

The 2D device simulator MEDICI, also from Technology Modeling Associates Inc., was used to predict the electrical characteristics of the device arrangements from TSUPREM-4. Here we use field hanging mobility models that have been benchmarked to the HP CMOS10 proces Iterative simulations with TSUPREM-4 and MEDICI were performed to determine the requirements in succession junction depth and channel doping profile to make secure proper threshold and subthreshold behavior. Fig. 1 exhibits the device structures resulting from these simulations for each generation from 035 [Mu]m down to 007 [Mu]m For [Lsubg] les than 015 [Mu]m retrograde channel doping profiles are necessityed to control the subthreshold characteristics.

Figs. 2 end 5 summarize the results of this scaling subject of attention Fig. 2 shows the scaling of [Tsubox] with [Lsubg] These sum of two units must scale together to achieve adequate performance improvement. Constant field scaling dictates that [Vsubdd] must decrease proportionally to [Tsubox] maintaining a peak oxide field of 4 MV/cm For example, this eventuates in [T.sub.ox] = 2.5 nm and [Vsubdd] = 1V for the [Lsubg] = 01 [Mu]m generation.

Fig. 3 present to views the scaling of effective channel extent (L.sub.eff]) and the source/drain extension junction silence ([X.sub.j]). For the 0.1-[Mu]m generation, [Lsubeff] is about 007 [Mu]m and [Xsubj] must be nearly 50 nm The series resistance of the source/drain extension must decrease steady as the junction depth also decreases. This requires higher doping flats in the extension region and carefully minimized spacer widths.

Fig. 4 indicates the scaling of threshold voltage ([Vsubt]) Here [Vsubt] is kept at 20% of [Vsubdd] to maintain adequate present drive. This yields [V.sub.t] = 02V for the 01-[Mu]m generation. Unfortunately, since off-state rife varies exponentially with [V.sub.t], reducing [Vsubt] leads to a great deal higher off-state leakage current (100 nA/[Mu]m for the 01-[Mu]m generation) than in present CMOS technologies. Here the simulations are tailored to predict the nominal leakage. Worst-case leakage would be approximately single order of magnitude higher for the 01-[Mu]m case.